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Matrox Solios eA/XA acquisition section 77

PSGs

Matrox Solios eA/XA Quad features four programmable synchronization

generators (PSGs), Matrox Solios eA/XA Dual features two, whereas Matrox Solios

eA/XA Single features one. The PSGs are responsible for managing all input and

output video timing, synchronization, trigger, timer, and user signals. The PSGs

on Matrox Solios eA/XA allow the board to adapt to many video standards. Each

PSG allows for independent acquisition from a video source. Therefore, Matrox

Solios eA/XA allows acquisition from up to four independent video sources,

depending on the board.

The phase-locked loop

The high-performance, low-jitter phase-locked loop (PLL) uses frequency

synthesis techniques to generate the clock signal in slave mode.

As a reference, the PLL uses the composite or horizontal video synchronization

signal supplied by the video source (line-locked mode).

Since the signal from the video source is used as a reference, the PLL can produce

a clock signal that is a multiple of it. If the video source supplies a clock signal

within the input range of the A/D converters, the PLL is bypassed to avoid adding

jitter to the supplied clock.

Specification

Operating frequency range 12 to 80 MHz

Jitter 4.6 nsec p-p absolute with RS-170 synchronization source

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VSync 924 Especificaciones Pagina 77