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Matrox Solios eCL/XCL acquisition section 65

Timers

Each PSG has four timers

. These timers can each generate a timer output signal

with up to two pulses; timer output signals can be used to control the exposure

time and other external events related to the video source (such as a strobe). The

timer output signals can be output using camera control signals or auxiliary output

signals (or auxiliary I/O signals in output mode).

Each PSG has two 24-bit timers (Timer 0 and 1) and two 16-bit timers (Timer 2

and 3). The 24-bit timers can count up to 16777215 clock ticks before resetting;

the 16-bit timers can count up to 65535 clock ticks before resetting.

The timers can use one of the following as a clock source:

• A clock based on an external pixel clock signal.

• A clock that is internally generated. Each timer can use its PSG’s clock generator,

which can generate a single clock with a programmable frequency of 0.8 to

100 MHz. Timers can only use the clock generator of their own PSG.

• A clock from an external source. In this case, you must define the appropriate

auxiliary input signal as a timer-clock input; the timer-clock input signal must

meet the specification of the auxiliary signal. The same timer-clock input can be

used to clock different timers of the same PSG.

• A clock based on another timer output of the same PSG. Timer 0 can use a clock

based on Timer 1, and Timer 1, 2, and 3 can use a clock based on Timer 0.

• A clock based on the HSYNC or VSYNC signal generated by the PSG.

To output a timer signal, use the MIL-Lite function MdigControl() with

M_IO_SOURCE + M_AUX_IOn

†

(or + M_CC_IOn

†

) set to M_TIMERm

†

Set up the timers using MdigControl() with M_TIMER_...

†

*. For the standard Camera Link speed Matrox Solios XCL dual-Base/single-Medium

boards (66 MHz), four timers have been available starting from version 100. Prior to

version 100, only two timers were available.

†. As of MIL 10.

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VSync 924 Especificaciones Pagina 65